Your author personally proofread this book about a hundred times, and so after four years of not hearing any
complaints, he was pretty sure that a perfect book had finally been published. But alas, recently some observant
readers have pointed out a few things. Here are 4 items as of May 2016:
1. In the chapter "A Few More Words on Arithmetic" (page 141 in the printed book) there is a diagram that shows how to
do subtraction in three steps. In the center of the top line, the box shows "0010 0101" and says it equals 21. Actually, it
equals 37. The correct binary for 21 would be "0001 0101" and should look like this:
There are two problems with the "Carry In" bit in the design of the CPU. Carry In is used as an extra input bit for Shift and
Add instructions.This is useful for things like adding numbers that are larger than 255. If it takes, for example, two bytes
to store each input number in RAM, then you have to add the right hand bytes first, then the left hand bytes. If the right
hand addition results in a carry, that needs to be input into the addition of the left hand bytes.
2. The first problem is, that every instruction also uses the adder to add one to the contents of the IAR. Carry In is never
needed for this. However, as designed, the Carry Flag is always connected, so if it is on, we will add two to the IAR
instead of one!
The solution is to add an enabler (a single AND gate) between Carry In and the ALU. This will only be turned on during
step 5 of the ALU instruction (the same time that Reg A is enabled) and thus will be off at all other times.
3. The second problem is that when the Carry Flag gets set (step 5 of ALU instruction again), its output then becomes
immediately available back at the input of the current ALU operation. If the new value of carry is different than it had
been, it can then affect the answer. To make sure this doesn't happen, we need to save the value of the Carry Flag
before step 5, and use that for the input during step 5. We will add a new memory bit called "Carry Temp" that goes
between the Carry Flag and the enabler we just added above. It will be set in step 4, the same time that the TMP register
gets set. Thus, the ALU instruction will have a carry input that cannot change during step 5.
The two fixes incorporated into the CPU diagram (Chapter: "The Third Great Invention") looks like this:
The bit that enables Carry In comes from step 5 of the ALU instruction as shown here in the diagram from the
chapter "The Arithmetic or Logic Instruction":
4. In the chapter "The Arithmetic or Logic Instruction," page 117 in the book, it shows that '001' is the SHL operation,
and that '010' is the SHR operation. It should be the other way around, as shown here: